1. Field of the Invention
The present invention relates to a memory composed of MOSFETs (i.e., metal-oxide-semiconductor field effect transistors) and, more particularly, to a technique which is effective for a dynamic type RAM (i.e., random access memory) made detective of changes in an address signal for generating a timing signal necessary for the operation of an internal circuit.
2. Description of the Prior Art
I, the Inventor, has conceived a pseudo-static type RAM, which is constructed to detect changes in an address signal for generating a variety of timing signals necessary for the operations of an internal circuit thereof, prior to the present invention. This pseudo-static type RAM has memory cells composed of capacitors for storing data in the form of charges and MOSFETs for address selections and has its peripheral circuits composed of CMOS (i.e., complimentary MOS) static type circuits. This RAM has such external characteristics as can deemed to be identical to those of the static RAM because, in response to the changes in the address signal detected, the various timing signals necessary therefor are generated.
In this case, the following problems are encountered, as has been revealed by my investigations. The changing timings of the individual address signals of plural bits fed to the RAM are caused to possibly fail to be synchronized to one another by the undesired timing discrepancies, which are encountered by a circuit itself such as a CPU (i.e., central processing unit) for generating those address signals, or by the unevenness in the signal delay of the printed circuit board. If the timing discrepancies (e.g., skews) are encountered in the changes in the address signals of plural bits fed to the RAM, there arises a fear that a word line selecting operation may be restarted by an address signal which changes with a delay after the word line selection is started. In case data to be read out from a dynamic type memory cell such as one MOSFET cell, the level of the holded data in the memory cell selected is changed to an insufficient level by the charge sharing which is caused between the capacitor of that memory cell and the capacitor existing in the data line with which the memory cell is connected. In other words, the data holded in the memory cell are substantially broken. As a result, the data at minute levels, which are read out from the memory cell, are amplified to the desired levels by a sense amplifier, as is well known in the art. The data thus amplified are rewritten in the memory cell.
If the word line selecting operations are started many times within a short period of time by the skews of the address signal, the switching of the word lines is executed in response thereto before the data levels being substantially broken by the read-out operation are rewritten in the corresponding memory cell with the status in which the data levels are amplified to the desired levels. This results is a serious problem that the stored data are broken.